1. Field of the Invention
The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to an improvement of a channel stopper region.
2. Description of the Related Art
Generally, in a semiconductor device, a field silicon oxide layer formed by a local oxidation of silicon (LOCOS) process partitions active areas of a semiconductor substrate (or well). Also, a channel stopper region having a higher impurity concentration of the same conductivity type as that of the semiconductor substrate is provided in the semiconductor substrate beneath the field silicon oxide layer. The channel stopper region enhances the threshold voltage of a parasitic MOS transistor formed by the semiconductor substrate, the field oxide layer and its overlying wiring layer, and enhances the punch-through breakdown voltage between impurity diffusion regions sandwiching the field silicon oxide layer, thus improving the isolation characteristics.
In a prior art method for forming a channel stopper region, the channel stopper region is formed in alignment with a field silicon oxide layer. In other words, the area of the channel stopper region coincides with that of the field silicon oxide layer. This will be explained later in detail.
In the prior art method, however, when an impurity diffusion region of an opposite conductivity type to that of the semiconductor substrate is provided so as to be in contact with a conductive contact plug, the impurity diffusion region is in contact with the channel stopper region. As a result, a capacitance caused by a PN junction formed by the channel stopper region and the impurity diffusion region which both have relatively high impurity concentrations is remarkably increased. This increases the parasitic capacitance of a conductive layer connected Lo this PN junction, thus reducing the operation of the device.